1. Field of the Invention
The present invention relates to a MOS (Metal Oxide Silicon) semiconductor device and its manufacturing method, and particularly to a semiconductor device with a suppressed-resistance contact structure and its manufacturing method.
2. Description of Related Art
With recent advances in design and process technology, it has become possible to manufacture high density integrated circuits. In parallel to the high integration, on-chip integrated circuits become faster and faster. In such environments, the salicide (self-aligned silicide) process, which forms a metal silicide film on the surface of the polysilicon layer of gate electrodes and on the surface of source-drain regions by the self-aligned technique, has great effect on reducing parasitic resistance of transistors, and hence is growing as an important technique governing the performance of the device.
FIG. 14 is a cross-sectional view showing a structure of an element of a conventional semiconductor device. In this figure, the reference numeral 101 designates a semiconductor substrate, 102 designates an isolation film, 103 designates a gate insulator, 104 designates a gate electrode, 1041 designates a polysilicon layer, 105 designates a sidewall insulator, 106 designates a source-drain region, 1042 and 107 designate a metal silicide film, 108 designates an interlayer insulating film, 109 designates a contact hole, 1010 designates a contact layer, 1011 designates a barrier metal, and 1012 designates a metal interconnection. The gate electrode 104 consists of the polysilicon layer 1041 and the metal silicide film 1042. As shown in FIG. 14, the metal silicide films 1042 and 107 are formed on the surface of the polysilicon layer 1041 and the source-drain region 106 to reduce resistance.
FIGS. 15 and 16 are cross-sectional views illustrating some steps of the manufacturing process of a conventional semiconductor device. Referring to FIG. 15, first, the isolation film 102 composed of silicon oxide is formed in the surface of the semiconductor substrate 101 to isolate individual active regions. Subsequently, a silicon oxide film is formed on the surface of the semiconductor substrate 101 in the active regions by thermal oxidation, followed by forming a polysilicon film on the silicon oxide. After that, the gate insulator 103 and the polysilicon layer 1041 are formed by patterning using a photoresist mask. FIG. 15 is a cross-sectional view showing the element of the semiconductor device at the end of the process step.
In FIG. 16, the reference numeral 1071 designates a metal film.
Referring to FIG. 16, the sidewall insulators 105 are formed by forming a silicon oxide film on the entire surface, followed by etching back. Then, the n-type source-drain region 106 is formed by ion implanting impurities such as phosphorus or arsenic, and by activating ion implanted impurities by heat treatment (in the case of p-type, boron or boron fluoride is implanted).
Subsequently, the metal film 1071 is formed on the entire surface, followed by forming the metal silicide films 1042 and 107 by causing reaction between the metal and silicon on the surface of the polysilicon layer 1041 and of the source-drain region 106 by applying heat treatment. FIG. 16 is a cross-sectional view showing a structure of the element of the semiconductor device at the end of the process step.
Subsequently, after removing the unreacted metal film 1071, the interlayer insulating film 108 composed of PSG (phospho-silicate glass) or BPSG (boro-phospho silicate glass) is formed on the entire surface, followed by forming the contact holes 109 reaching the gate electrode 104 and the source-drain region 106.
After that, the element of the semiconductor device as shown in FIG. 14 is completed by successively forming and patterning a Ti layer constituting the contact layer 1010, a TiN layer constituting the barrier metal 1011 and a metal film constituting the metal interconnections 1012 on the exposed surface.
Higher-speed devices of today, however, require devices with lower resistance. For example, Japanese patent application laid-open No. 11-330271/1999 discloses a technique for reducing the contact resistance at the interface between the silicide film and the semiconductor substrate by forming a silicide film after making the surface of the source-drain region amorphous after forming the source-drain regions of nMOS transistors. Japanese patent application laid-open No. 11-330271/1999 reduces it by implanting impurities with the same conductivity type as that of the source-drain regions again after forming a silicide film on the surface of the source-drain regions. Japanese patent application laid-open No. 11-330271/1999 reduces it by controlling the condition of impurity implantation into the source-drain regions.
The scale down of the device, however, presents a problem of reducing the diameters of the contact holes, thereby reducing the contact areas between the con-tact layers and the metal silicide films, and increasing the resistance between them. Furthermore, the heat treatment after forming the metal interconnections will diffuse the impurities such as arsenic (As) or phosphorus (P) from the source-drain regions of the nMOS transistors, which presents a problem in that the diffused impurities segregates on the interfaces between the contact layers and the metal silicide films, and hence increases the interface resistance between the contact layers and the metal silicide films.
In particular, as for a system LSI that comprises transistors of both DRAM memory cells and logic circuits formed on the same substrate, since the heat treatment for forming the capacitors of the DRAM memory cells is applied after the metallization for interconnecting the transistors of the logic circuits, the impurities are likely to diffuse from the source-drain regions of the nMOS transistors, presenting a problem of increasing the interface resistance between the contact layers and the metal silicide films.
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a semiconductor device and its manufacturing method capable of reducing the contact resistance at the interfaces between the contact layers and the metal silicide films in spite of the scale down of semiconductor integrated circuits, thereby achieving higher-speed devices.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first active region of a first conductivity type disposed in a main surface of a semiconductor substrate, the first active region being surrounded by an isolation film; first source region and drain region of a second conductivity type formed in the main surface of the first active region, the first source region and drain region being separated by a predetermined distance; a first gate electrode formed on the main surface of the first active region via a gate insulator, the first gate electrode facing a region between the first source region and drain region; a metal silicide layer and an impurity region of the first conductivity type that are formed on the surface of the first source region and drain region, and thinner than the first source region and drain region; and interconnections connected to the first source region and drain region, respectively.
Here, the impurity region of the first conductivity type may have a thickness equal to or less than half a thickness of the metal silicide layer.
The impurity region of the first conductivity type may be formed only at neighborhood of interfaces between the interconnections and the first source region and drain region.
The interconnections may each consist of a stack of a contact layer, a barrier metal and a metal.
The semiconductor device may further comprise: a second active region of the first conductivity type disposed in an area different from an area of the first active region in the main surface of the semiconductor substrate; second source region and drain region of the second conductivity type formed in the main surface of the second active region, the second source region and drain region being separated by a predetermined distance; a second gate electrode formed on the main surface of the second active region via a gate insulator, the second gate electrode facing a region between the second source region and drain region; and a capacitor connected to one of the second source region and drain region.
According to a second aspect of the present invention, there is provided a manufacturing process of a semiconductor device comprising the steps of: forming an isolation film on a main surface of a semiconductor substrate; forming a first gate electrode on a main surface of a first active region of a first conductivity type of the semiconductor substrate via a gate insulator, the first active region being surrounded by the isolation film; forming first source region and drain region of a second conductivity type in the main surface of the first active region, the first source region and drain region being separated by a predetermined distance with interposing between them an area facing the first gate electrode; forming a metal silicide layer in the main surface of the first source region and drain region, the metal silicate layer being thinner than the first source region and drain region; forming an impurity region of the first conductivity type in the main surface of the first source region and drain region, the impurity region being thinner than the first source region and drain region; forming a first interlayer insulating film on an entire surface; forming first contact holes in the first interlayer insulating film such that the first contact holes reaching the first source region and drain region; and forming interconnections connected to the first source region and drain region through the first contact holes.
Here, the impurity region of the first conductivity type may have a thickness equal to or less than half a thickness of the metal silicide layer.
The step of forming the impurity region of the first conductivity type comprises the substeps of: forming on the entire surface an insulating film after the step of forming the metal silicide layer on the main surface of the first source region and drain region, and before the step of forming the first interlayer insulating film; and ion implanting impurities of the first conductivity type through a surface of the insulating film.
The step of forming the impurity region of the first conductivity type may comprise the substep of: ion implanting impurities of the first conductivity type into the entire surface after the step of forming the first contact holes, and before the step of forming the interconnections.
The step of forming the impurity region of the first conductivity type may comprise the substeps of: burying an organic resin into the first contact holes after the step of forming the first contact holes, and before the step of ion implanting the impurities; and removing the organic resin before the step of forming the interconnections.
The first interlayer insulating film may be extended to the second active region, wherein the manufacturing process may further comprise the steps of: forming via a gate insulator a second gate electrode on a second active region of the first conductivity type disposed in an area different from an area of the first active region in the main surface of the semiconductor substrate; forming second source region and drain region of the second conductivity type in the main surface of the second active region, the second source region and drain region being separated by a predetermined distance and interposing between them a region facing the gate electrode; forming a second interlayer insulating film on the entire surface after the step of forming the interconnections; forming a second contact hole in the first interlayer insulating and in the second interlayer insulating film, the second contact hole reaching one of the second source region and drain region; and forming a capacitor connected to one of the second source region and drain region through the second contact hole.